In simultaneously forming a plurality of contact holes to connect an upper layer and a lower layer in a semiconductor device by dry etching, the holes having a relatively smaller opening area are likely to relatively lower etching rate, which easily causes insufficient etching. This may lead to the increase in contact resistance. In contrast, the holes having a relatively larger opening area are likely to relatively increase etching rate, which easily causes overetching. This may cause an element (e.g., a substrate) lower than the layer which is a target to be connected with the upper layer to be short-circuited with the upper layer.